Digital Design Engineering Manager manages daily activities in the digital design of integrated circuits and related development. Leads all phases of physical design including floor planning, clock synthesis, timing optimization and signal integrity. Being a Digital Design Engineering Manager requires a bachelor's degree. Typically reports to a senior management. The Digital Design Engineering Manager manages subordinate staff in the day-to-day performance of their jobs. True first level manager. Ensures that project/department milestones/goals are met and adhering to approved budgets. Has full authority for personnel actions. To be a Digital Design Engineering Manager typically requires 5 years experience in the related area as an individual contributor. 1 - 3 years supervisory experience may be required. Extensive knowledge of the function and department processes. (Copyright 2024 Salary.com)
USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.
*This position is based in Arlington, VA. Hybrid work options are available *
The Computational Systems and Technology division at ISI is a leader in disrupting and advancing the fields of digital design, computer architecture and EDA tooling. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.
CST staff can be found:
Our success is based on investing in our staff through a culture centered on:
We are looking for highly talented, motivated technical leaders to join our team. This position will lead research and propose major innovations in domain specific computing targeting ASICs and FPGAs. Research and develop high speed, compact on-chip communication and switching mechanisms that scale to full device solutions. Collaborate with team members developing custom EDA tools to perform design space exploration of custom architectures across unique performance parameters. Be an active member of a fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. The successful candidate will also collaborate with peers within the group and across ISI; publish results in top tier conferences; and contribute to and lead proposals efforts.
Position specific JOB QUALIFICATIONS:
Preferred Job Qualifications:
The annual base salary range for this position is $148,701 - $180,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate’s work experience, education/training, key skills, internal peer equity, federal, state and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.
The University of Southern California values diversity and is committed to equal opportunity in employment.